Silicon wafers (hereinafter, it may also called “Si wafer”) to be a material for semiconductor devices can be generally manufactured in such a way that a silicon single crystal is grown by the Czochralski method (Czochralski Method: hereinafter, it may also called the “CZ method”) and the obtained silicon single crystal is subjected to processing steps of slicing, polishing, or the like.
The silicon single crystal grown by the CZ method in this way may cause an oxidation-induced stacking fault called OSF, which is generated in a ring shape when being subjected to thermal oxidation processing (for example, at 1100 degrees C.×for 2 hours). It has become clear that a micro defect (hereinafter, called Grown-in defect) which is formed during the crystal growth and has harmful effects on device performance exists other than OSF.
Accordingly, there has been recently disclosed a manufacturing method of the single crystal for obtaining wafers in which these defects are reduced as less as possible, in Japanese Unexamined Patent Publication (Kokai) No. H11-79889, for example.
In letting a pulling rate during the single crystal growth be V (mm/min), and a mean value of a temperature gradient inside the crystal along a direction of a pulling axis be G (degree C./mm) in a temperature range from a silicon melting point to 1350 degrees C., according to the method disclosed by Japanese Unexamined Patent Publication (Kokai) No. H11-79889, FIG. 5 shows a relation between a pulling rate and a defect generation distribution when the single crystal is grown while changing V/G.
It has generally known that a temperature distribution G in the single crystal is dependent on a structure inside a CZ furnace (hereinafter, called hot zone) and thus the distribution will be hardly changed even when the pulling rate is changed. For this reason, V/G will correspond to only the change in the pulling rate if the CZ furnaces with the same structure are used. Namely, there is approximately a direct proportion relation between V and V/G. Hence, the pulling rate V is used for a vertical axis shown in FIG. 5.
In a region where V is relatively high, vacancy-type Grown-in defects called COP (Crystal Originated Particle) and FPD (Flow Pattern Defect) where vacancy-type point defects called a Vacancy (Vacancy: hereinafter, called Va) are gathered exist in all the areas of the crystal, and it is called a Va-Rich region.
OSFs are generated in a ring shape from the periphery of the crystal when V becomes slightly slower than this, OSFs are shrunk toward the center thereof as V becomes slower, and OSFs are finally annihilated in the center of the crystal.
When V is further slowed down, a Neutral (hereinafter, called N) region where excess and deficiency of Va and interstitial-type point defects called interstitial silicon (Interstitial Silicon: hereinafter, called I) is small exists. It has become clear that the defects do not exist or existence of the defects cannot be confirmed by a current defect detection method since the concentration of Va and I in this N-region is not more than a saturated concentration although there are deviations of Va and I.
The N-region is classified into an Nv region where Va is dominant and an Ni region where I is dominant.
When V is still further slowed down, I becomes supersaturated, and thus defects of L/D (Large Dislocation: abbreviation of interstitial dislocation loop, for example LSEPD, LEPD, or the like) considered to be a dislocation loop where I are gathered exist in lower density; it is called an I-Rich region.
When the Grown-in defect which exists in the Va-Rich region, the OSF region, or the I-Rich region appears in the wafer front surface, it has harmful effects on device properties, such as degradation of an oxide dielectric breakdown voltage or the like in forming a MOS (Metal Oxide Semiconductor) structure of the device, so that it is desired that there is no such defects in the wafer front surface layer.
Incidentally, oxygen of about 7×1017 to 10×1017 atoms/cm3 (use the conversion factor based on JEITA: Japan Electronic Industry Development Association) is typically included in the Si wafer in a supersaturated state. For that reason, a large amount of Grown-in oxide precipitate nuclei exist in the Si wafer, and when the Si wafer is subjected to heat treatment during device processes or the like, supersaturation oxygen in the Si wafer precipitates as the oxide precipitates, and the Grown-in oxide precipitate nucleus grows to become obvious. The oxide precipitate like this is called BMD (Bulk Micro Defect).
Generation of this BMD in the device active region in the wafer causes problems since it has harmful effects on device properties, such as junction leakages, whereas it is effective to serve as a gettering site for capturing metal impurities mixed during the device processes as far as it exists in a bulk other than the device active region.
For that reason, in manufacturing the Si wafer, while the BMD must be formed into the bulk of the wafer, the vicinity of the wafer front surface which is the device active region must maintain a defect-free region (Denuded Zone; hereinafter, also called DZ layer) where neither the BMD nor the Grown-in defect exists.
In recent years, to these requests, there is disclosed a method for manufacturing a wafer in Japanese Unexamined Patent Publication (Kokai) No. 2002-353225, in which an ingot is manufactured in which growth of COP is suppressed and oxygen precipitation is promoted simultaneously by doping nitrogen when the silicon single crystal is grown by the CZ method, and a mirror wafer sliced from the ingot and polished is annealed at a high temperature for a long time (for example, at 1200 degrees C. for 1 hour) in an argon gas atmosphere to thereby annihilate COP near a surface layer and form the BMD in the bulk.
According to the method, the wafer is loaded into a heat treatment furnace at, for example, 700 degrees C., is heated at a rate of temperature increase of 5 degrees C./min up to 1000 degrees C. and at the rate of temperature increase of 3 degrees C./min from 1000 to 1200 degrees C. to keep it at 1200 degrees C. for 1 hour and subsequently is taken out from the furnace after lowering the temperature to 700 degrees C.
The reason why the rate of temperature increase from 700 to 1000 degrees C. is 5 degrees C./min is that if the temperature increase is larger than 5 degrees C./min, the sufficient BMD cannot be formed since the Grown-in oxide precipitate nuclei formed during the ingot pull-up process is partially dissolved during the temperature increase process.
However, although this method is effective in annihilating defects in the surface layer since annealing is performed at a high temperature and for a long time, it tends to increase processing cost and cause contamination during the heat treatment. Additionally, there is a problem that a slip is easy to be generated because of high temperature. Further, the BMD grows largely because of the heat treatment at a high temperature and for a long time, so that degradation in mechanical strength of the wafer is caused and the slip tends to be generated during the device process. Alternatively, there have been problems of easily causing plastic deformation or the like.
Meanwhile, a method for forming a shallow trench to isolate devices, called shallow trench isolation (Shallow Trench Isolation: hereinafter, called STI) is adopted for most of the devices in recent years for device isolation. FIG. 6 schematically shows a cross section thereof.
After a shallow trench 31 is formed from a front surface of a silicon wafer 30 using anisotropic etching, a SiO2 32 is buried by CVD (Chemical Vapour Deposition), and thereby an STI 33 is formed. A device is formed between STIs 33.
In typical devices, an N-channel MOS transistor 34 and a P-channel MOS transistor 35 are formed, and both are isolated by the STI 33.
Since SiO2 with a volume larger than that of Si is buried inside of this STI 33, tensile stress is generated in an interface between the STI 33 and the silicon in general, so that there have been problems that deformation of the Si wafer 30 and a slip are generated due to this stress. This stress is most remarkably generated at the bottom of the STI 33.
In order to relieve the stress generated at the bottom of the STI, it is known that it is extremely effective to form a steep and the high-density BMD and a strained layer in a position which is under the STI and as close as possible to the STI, and there is proposed a method in, for example, Japanese Unexamined Patent Publication (Kokai) No. H9-162278, in which oxygen atoms are introduced into the position under the STI region by ion implantation, heat treatment is subsequently performed to deposit the implanted oxygen atoms, and thereby the BMDs are formed directly under the STI.
Generally, in order to annihilate defects associated with oxygen, such as COP and OSF nucleus, oxide precipitates, or the like, since it is necessary to reduce an oxygen concentration to a solubility limit or less, the oxygen concentration is reduced to the solubility limit or less by reducing the oxygen concentration in the surface layer by utilizing out-diffusion of oxygen.
As a result, distribution of density and size of BMD which is the oxide precipitate in a depth direction becomes a distribution of making an oxygen concentration profile from the surface layer into a template, namely, an error functional distribution.
If the distribution in the depth direction of the BMD is the error functional distribution, a sufficiently steep BMD profile cannot be obtained to relieve the stress in the STI bottom. Additionally, when considering an oxygen concentration of radial distribution in the wafer in a radial direction, a width of the DZ layer in a region having a high oxygen concentration becomes narrow, so that it is necessary to make the DZ width in this region deeper than a depth of the STI. Meanwhile, since the width of the DZ layer in a region having a low oxygen concentration in radial direction becomes wider, the BMD can be formed only in a position far from the STI bottom, so that there has been a problem that the stress in the STI bottom cannot be relieved further.
The larger the radial variation of the oxygen concentration and the variation thereof among the wafers, the more remarkable this problem becomes.
Moreover, the oxygen concentration is reduced by the out-diffusion of oxygen, so that there has also been a problem that the mechanical strength of the DZ layer formed in the surface layer is also degraded.
As a method for solving the problems that the BMD size is increased due to the above-described high temperature and long time heat treatment, and the steep BMD profile is not obtained due to utilizing the out-diffusion of oxygen, a method for performing RTP (Rapid Thermal Process) processing to the Si wafer can be considered.
This RTP processing is a heat treatment method characterized in that the Si wafer is rapidly heated from a room temperature at a rate of temperature increase of, for example, 50 degrees C./sec in an atmosphere forming a nitride, such as N2, NH3, or the like, or a mixed gas atmosphere of these gases with an atmosphere of not forming the nitride, such as Ar, H2, or the like, and is held at a temperature of about 1200 degrees C. for about a few tens sec, and subsequently is rapidly cooled down at a rate of temperature decrease of, for example, 50 degrees C./sec.
A mechanism that the BMD is formed by performing the oxygen precipitation heat treatment after the RTP processing is described in detail in Japanese Unexamined Patent Publication (Kokai) No. 2001-203210 and Published Japanese Translation No. 2001-503009 of the PCT International Application.
Here, the BMD forming mechanism will be described simply.
First, in the RTP processing, injection of Va is generated from the wafer surface in keeping high temperature of, for example, 1200 degrees C. in the N2 atmosphere, and re-distribution due to diffusion of Va, and annihilation with I are caused while cooling down the wafer at a rate of temperature decrease of 5 degrees C./sec in a temperature range of 1200 degrees C. to 700 degrees C. As a result, it becomes a state where Va is unevenly distributed in the bulk.
If the wafer in such a state is subjected to heat treatment at, for example, 800 degrees C., oxygen clusters quickly in the high Va concentration region, but oxygen clustering is not generated in the low Va concentration region.
If heat treatment is subsequently performed for a certain period of time at, for example, 1000 degrees C. in this state, the clustered oxygen grows and the BMD is formed. As described above, if the oxygen precipitation heat treatment is applied to the Si wafer after the RTP processing, the BMD which has the distribution in a wafer depth direction will be formed according to a concentration profile of Va formed by the RTP processing.
Hence, a desired Va concentration profile is formed in the Si wafer by controlling conditions of the atmosphere, the highest temperature, the holding time or the like of the RTP processing, and thereafter, by performing the oxygen precipitation heat treatment to the Si wafer obtained, Si wafer having a desired DZ width and a desired BMD profile in the depth direction is manufactured.
As described above, in the case of the RTP processing, although the DZ layer is not formed utilizing the out-diffusion of oxygen, Va is newly injected by the RTP processing to form the DZ layer utilizing out-diffusion of this Va, so that the steep BMD cannot be formed fundamentally.
Additionally, a point that the DZ layer width varies due to the variation in oxygen concentration is not different from a method of utilizing the out-diffusion of oxygen, either.
Meanwhile, since the RTP processing is short-time heat treatment, there is an advantage that the BMD size does not increase. However, there is a problem that when the Grown-in defects such as COP or L/D exist in the Si wafer to be the material, these types of defects cannot be sufficiently annihilated because the heat treatment is performed for an extremely short time.
Namely, it is possible to secure a region where the BMD is not generated to a certain depth in the surface layer when the Si wafer having the Grown-in defects is subjected to the RTP processing, but when speaking of the Grown-in defects, although the Grown-in defects can be annihilated in a very shallow region of the surface layer by the RTP processing, the Grown-in defects cannot be annihilated in a region deeper than that to result in a state where they still exist, and thus the whole device active region cannot be made defect-free. For this reason, there have also been problems that device properties are degraded.
In addition, another method for forming the DZ layer in the surface layer is disclosed in Published Japanese Translation No. 2001-517871 of the PCT International Application.
This is a method in which a light pulse is irradiated from the wafer front surface for about 1 to 5 sec to heat up the front surface at about 1000 degrees C. while the wafer back surface is fixed to a heat sink to keep it at a temperature of less than 900 degrees C., thereby a temperature distribution is decreased from the wafer front surface toward the wafer back surface, and thus the DZ layer is formed near the front surface. However, even such a method could not make the BMD profile of the interface between the DZ layer and a BMD layer steep.